ESBMC
Efficient SMT-based Context-Bounded Model Checker
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driver_types.h
Go to the documentation of this file.
1#ifndef __DRIVER_TYPES_H__
2#define __DRIVER_TYPES_H__
3
4#include "host_defines.h"
5
6#ifdef __cplusplus
7
8extern "C"
9{
10#endif
11
12 /*
13 * \defgroup CUDART_TYPES Data types used by CUDA Runtime
14 * \ingroup CUDART
15 */
16
17#if !defined(__CUDA_INTERNAL_COMPILATION__)
18
19# include <limits.h>
20# include <stddef.h>
21
30
31 /*
32 * CUDA stream
33 */
34
35 /*DEVICE_BUILTIN*/
36 typedef struct CUstream_st *cudaStream_t;
37
38 typedef __device_builtin__ struct CUevent_st *cudaEvent_t;
39
41 {
42 char name[256];
47 size_t memPitch;
50 int maxGridSize[3];
53 int major;
54 int minor;
71 int maxTexture2D[2];
77 int maxTexture3D[3];
85 int maxSurface2D[2];
86 int maxSurface3D[3];
121 };
122
123 /*
124 * CUDA device attributes
125 */
127 {
129 1,
137 8,
139 9,
143 11,
145 12,
151 16,
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156 19,
158 20,
166 27,
168 28,
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179 36,
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184 39,
187 41,
189 42,
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193 45,
195 46,
197 47,
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204 51,
206 52,
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210 54,
218 61,
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244 74,
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248 76,
250 77,
252 78,
254 79,
256 80,
258 81,
260 82,
263 83,
265 cudaDevAttrMultiGpuBoardGroupID =
266 85
268 };
269
270# ifdef __cplusplus
271}
272
273# endif
274
275#endif
276
277#endif /* !__DRIVER_TYPES_H__ */
cudaDevAttrUnifiedAddressing
Device shares a unified address space with the host.
Definition driver_types.h:186
cudaDevAttrMaxSurface2DLayeredWidth
Maximum 2D layered surface width.
Definition driver_types.h:221
cudaDevAttrMaxTexture1DLayeredWidth
Maximum 1D layered texture width.
Definition driver_types.h:188
cudaMemcpyHostToHost
Host -> Host.
Definition driver_types.h:24
cudaDevAttrMaxRegistersPerBlock
Maximum number of 32-bit registers available per block.
Definition driver_types.h:144
cudaDevAttrTexturePitchAlignment
Pitch alignment requirement for textures.
Definition driver_types.h:203
cudaDevAttrAsyncEngineCount
Number of asynchronous engines.
Definition driver_types.h:185
cudaDevAttrMaxTextureCubemapWidth
Maximum cubemap texture width/height.
Definition driver_types.h:205
cudaDevAttrMultiProcessorCount
Number of multiprocessors on device.
Definition driver_types.h:150
cudaDevAttrMaxSurfaceCubemapLayeredWidth
Maximum cubemap layered surface width.
Definition driver_types.h:229
cudaDevAttrComputeCapabilityMinor
Minor compute capability version number.
Definition driver_types.h:247
cudaDevAttrIntegrated
Device is integrated with host memory.
Definition driver_types.h:154
cudaDevAttrMaxSurfaceCubemapWidth
Maximum cubemap surface width.
Definition driver_types.h:227
cudaDevAttrMaxTexture3DDepthAlt
Alternate maximum 3D texture depth.
Definition driver_types.h:200
cudaDevAttrMaxGridDimZ
Maximum grid dimension Z.
Definition driver_types.h:135
cudaDevAttrMaxSurface2DLayeredLayers
Maximum layers in a 2D layered surface.
Definition driver_types.h:225
cudaDevAttrMaxSharedMemoryPerBlock
Maximum shared memory available per block in bytes.
Definition driver_types.h:136
cudaDevAttrMaxTexture2DMipmappedWidth
Maximum mipmapped 2D texture width.
Definition driver_types.h:241
cudaDevAttrLocalL1CacheSupported
Device supports caching locals in L1.
Definition driver_types.h:255
cudaDevAttrCanMapHostMemory
Device can map host memory into CUDA address space.
Definition driver_types.h:155
cudaMemcpyDeviceToHost
Device -> Host.
Definition driver_types.h:26
cudaDevAttrMaxTexture3DHeight
Maximum 3D texture height.
Definition driver_types.h:163
cudaDevAttrMaxSharedMemoryPerMultiprocessor
Maximum shared memory available per multiprocessor in bytes.
Definition driver_types.h:257
cudaDevAttrMaxGridDimX
Maximum grid dimension X.
Definition driver_types.h:133
cudaDevAttrIsMultiGpuBoard
Device is on a multi-GPU board.
Definition driver_types.h:264
cudaDevAttrMaxGridDimY
Maximum grid dimension Y.
Definition driver_types.h:134
cudaDevAttrMaxTexture3DWidth
Maximum 3D texture width.
Definition driver_types.h:162
cudaDevAttrMaxTexture1DWidth
Maximum 1D texture width.
Definition driver_types.h:159
cudaDevAttrComputeMode
Compute mode (See cudaComputeMode for details).
Definition driver_types.h:157
cudaDevAttrMaxThreadsPerBlock
Maximum number of threads per block.
Definition driver_types.h:128
cudaDevAttrPciBusId
PCI bus ID of the device.
Definition driver_types.h:175
cudaDevAttrL2CacheSize
Size of L2 cache in bytes.
Definition driver_types.h:182
cudaDevAttrMaxSurfaceCubemapLayeredLayers
Maximum layers in a cubemap layered surface.
Definition driver_types.h:231
cudaDevAttrMaxBlockDimY
Maximum block dimension Y.
Definition driver_types.h:131
cudaDevAttrMaxSurface1DWidth
Maximum 1D surface width.
Definition driver_types.h:211
cudaDevAttrMaxTexture2DGatherHeight
Maximum 2D texture height if cudaArrayTextureGather is set.
Definition driver_types.h:194
cudaDevAttrMemoryClockRate
Peak memory clock frequency in kilohertz.
Definition driver_types.h:178
cudaDevAttrMaxTexture2DLinearWidth
Maximum 2D linear texture width.
Definition driver_types.h:235
cudaDevAttrTotalConstantMemory
Memory available on device for constant variables in a CUDA C kernel in bytes.
Definition driver_types.h:138
cudaDevAttrMaxSurface2DWidth
Maximum 2D surface width.
Definition driver_types.h:212
cudaDevAttrGpuOverlap
Device can possibly copy memory and execute a kernel concurrently.
Definition driver_types.h:148
cudaDevAttrMaxBlockDimX
Maximum block dimension X.
Definition driver_types.h:130
cudaDevAttrTccDriver
Device is using TCC driver model.
Definition driver_types.h:177
cudaDevAttrWarpSize
Warp size in threads.
Definition driver_types.h:141
cudaDevAttrMaxSurface3DHeight
Maximum 3D surface height.
Definition driver_types.h:215
enum __device_builtin__ cudaDeviceAttr
Definition driver_types.h:127
cudaMemcpyHostToDevice
Host -> Device.
Definition driver_types.h:25
cudaDevAttrMaxSurface3DDepth
Maximum 3D surface depth.
Definition driver_types.h:216
cudaMemcpyDeviceToDevice
Device -> Device.
Definition driver_types.h:27
cudaDevAttrEccEnabled
Device has ECC support enabled.
Definition driver_types.h:174
enum __device_builtin__ cudaMemcpyKind
Definition driver_types.h:23
cudaDevAttrMaxTexture3DHeightAlt
Alternate maximum 3D texture height.
Definition driver_types.h:198
cudaDevAttrPciDeviceId
PCI device ID of the device.
Definition driver_types.h:176
cudaDevAttrComputeCapabilityMajor
Major compute capability version number.
Definition driver_types.h:245
cudaDevAttrMaxPitch
Maximum pitch in bytes allowed by memory copies.
Definition driver_types.h:142
cudaDevAttrMaxTexture1DLayeredLayers
Maximum layers in a 1D layered texture.
Definition driver_types.h:190
cudaDevAttrMaxTexture2DLayeredLayers
Maximum layers in a 2D layered texture.
Definition driver_types.h:169
cudaDevAttrMaxTexture3DWidthAlt
Alternate maximum 3D texture width.
Definition driver_types.h:196
cudaDevAttrMaxBlockDimZ
Maximum block dimension Z.
Definition driver_types.h:132
cudaDevAttrMaxTexture3DDepth
Maximum 3D texture depth.
Definition driver_types.h:164
__device_builtin__ struct CUevent_st * cudaEvent_t
Definition driver_types.h:38
cudaDevAttrMaxSurface2DLayeredHeight
Maximum 2D layered surface height.
Definition driver_types.h:223
cudaDevAttrManagedMemory
Device can allocate managed memory on this system.
Definition driver_types.h:262
cudaDevAttrMaxTexture2DLinearPitch
Maximum 2D linear texture pitch in bytes.
Definition driver_types.h:239
cudaDevAttrConcurrentKernels
Device can possibly execute multiple kernels concurrently.
Definition driver_types.h:172
cudaDevAttrMaxTexture2DGatherWidth
Maximum 2D texture width if cudaArrayTextureGather is set.
Definition driver_types.h:192
cudaDevAttrMaxTextureCubemapLayeredLayers
Maximum layers in a cubemap layered texture.
Definition driver_types.h:209
cudaDevAttrSurfaceAlignment
Alignment requirement for surfaces.
Definition driver_types.h:171
cudaDevAttrMaxRegistersPerMultiprocessor
Maximum number of 32-bit registers available per multiprocessor.
Definition driver_types.h:259
cudaDevAttrMaxSurface1DLayeredWidth
Maximum 1D layered surface width.
Definition driver_types.h:217
cudaDevAttrMaxTexture2DWidth
Maximum 2D texture width.
Definition driver_types.h:160
cudaDevAttrClockRate
Peak clock frequency in kilohertz.
Definition driver_types.h:146
cudaDevAttrGlobalMemoryBusWidth
Global memory bus width in bits.
Definition driver_types.h:180
cudaDevAttrMaxTexture2DMipmappedHeight
Maximum mipmapped 2D texture height.
Definition driver_types.h:243
cudaDevAttrGlobalL1CacheSupported
Device supports caching globals in L1.
Definition driver_types.h:253
cudaDevAttrMaxSurface3DWidth
Maximum 3D surface width.
Definition driver_types.h:214
cudaDevAttrMaxTexture2DHeight
Maximum 2D texture height.
Definition driver_types.h:161
cudaDevAttrMaxTexture1DLinearWidth
Maximum 1D linear texture width.
Definition driver_types.h:233
cudaDevAttrMaxSurface2DHeight
Maximum 2D surface height.
Definition driver_types.h:213
cudaDevAttrMaxTexture2DLayeredHeight
Maximum 2D layered texture height.
Definition driver_types.h:167
cudaDevAttrMaxTexture2DLayeredWidth
Maximum 2D layered texture width.
Definition driver_types.h:165
struct CUstream_st * cudaStream_t
Definition driver_types.h:36
cudaDevAttrMaxTexture2DLinearHeight
Maximum 2D linear texture height.
Definition driver_types.h:237
cudaDevAttrKernelExecTimeout
Specifies whether there is a run time limit on kernels.
Definition driver_types.h:152
cudaDevAttrPciDomainId
PCI domain ID of the device.
Definition driver_types.h:202
cudaDevAttrMaxTextureCubemapLayeredWidth
Maximum cubemap layered texture width/height.
Definition driver_types.h:207
cudaDevAttrMaxThreadsPerMultiProcessor
Maximum resident threads per multiprocessor.
Definition driver_types.h:183
cudaDevAttrMaxSurface1DLayeredLayers
Maximum layers in a 1D layered surface.
Definition driver_types.h:219
cudaDevAttrStreamPrioritiesSupported
Device supports stream priorities.
Definition driver_types.h:251
cudaDevAttrTextureAlignment
Alignment requirement for textures.
Definition driver_types.h:147
cudaDevAttrMaxTexture1DMipmappedWidth
Maximum mipmapped 1D texture width.
Definition driver_types.h:249
#define __device_builtin__
Definition host_defines.h:120
Definition driver_types.h:41
int asyncEngineCount
Number of asynchronous engines.
Definition driver_types.h:101
int unifiedAddressing
Device shares a unified address space with the host.
Definition driver_types.h:102
int maxTexture1DLayered[2]
Maximum 1D layered texture dimensions.
Definition driver_types.h:80
int maxTexture2DGather[2]
Maximum 2D texture dimensions if texture gather operations have to be performed.
Definition driver_types.h:75
int canMapHostMemory
Device can map host memory with cudaHostAlloc/cudaHostGetDevicePointer.
Definition driver_types.h:64
int maxThreadsPerBlock
Maximum number of threads per block.
Definition driver_types.h:48
char name[256]
ASCII string identifying device.
Definition driver_types.h:42
int maxTexture1DLinear
Maximum size for 1D textures bound to linear memory.
Definition driver_types.h:69
int maxTexture1D
Maximum 1D texture size.
Definition driver_types.h:67
int deviceOverlap
Device can concurrently copy memory and execute a kernel.
Definition driver_types.h:58
size_t texturePitchAlignment
Pitch alignment requirement for texture references bound to pitched memory.
Definition driver_types.h:56
int multiProcessorCount
Number of multiprocessors on device.
Definition driver_types.h:60
size_t memPitch
Maximum pitch in bytes allowed by memory copies.
Definition driver_types.h:47
int streamPrioritiesSupported
Device supports stream priorities.
Definition driver_types.h:109
int maxSurface3D[3]
Maximum 3D surface dimensions.
Definition driver_types.h:86
size_t textureAlignment
Alignment requirement for textures.
Definition driver_types.h:55
int minor
Minor compute capability.
Definition driver_types.h:54
int isMultiGpuBoard
Device is on a multi-GPU board.
Definition driver_types.h:118
int computeMode
Compute mode (See cudaComputeMode).
Definition driver_types.h:66
int globalL1CacheSupported
Device supports caching globals in L1.
Definition driver_types.h:110
int pciDeviceID
PCI device ID of the device.
Definition driver_types.h:97
int maxTexture2DLayered[3]
Maximum 2D layered texture dimensions.
Definition driver_types.h:81
int integrated
Device is integrated as opposed to discrete.
Definition driver_types.h:63
int maxTexture2D[2]
Maximum 2D texture dimensions.
Definition driver_types.h:71
int multiGpuBoardGroupID
Unique identifier for a group of devices on the same multi-GPU board.
Definition driver_types.h:119
int major
Major compute capability.
Definition driver_types.h:53
int maxTexture1DMipmap
Maximum 1D mipmapped texture size.
Definition driver_types.h:68
size_t sharedMemPerMultiprocessor
Shared memory available per multiprocessor in bytes.
Definition driver_types.h:112
int maxSurface1DLayered[2]
Maximum 1D layered surface dimensions.
Definition driver_types.h:87
int maxTexture3D[3]
Maximum 3D texture dimensions.
Definition driver_types.h:77
int maxTexture3DAlt[3]
Maximum alternate 3D texture dimensions.
Definition driver_types.h:78
int ECCEnabled
Device has ECC support enabled.
Definition driver_types.h:95
int maxTexture2DLinear[3]
Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory.
Definition driver_types.h:73
int maxGridSize[3]
Maximum size of each dimension of a grid.
Definition driver_types.h:50
size_t sharedMemPerBlock
Shared memory available per block in bytes.
Definition driver_types.h:44
int regsPerBlock
32-bit registers available per block
Definition driver_types.h:45
int warpSize
Warp size in threads.
Definition driver_types.h:46
int concurrentKernels
Device can possibly execute multiple kernels concurrently.
Definition driver_types.h:93
size_t surfaceAlignment
Alignment requirements for surfaces.
Definition driver_types.h:92
int maxThreadsDim[3]
Maximum size of each dimension of a block.
Definition driver_types.h:49
int maxThreadsPerMultiProcessor
Maximum resident threads per multiprocessor.
Definition driver_types.h:107
size_t totalGlobalMem
Global memory available on device in bytes.
Definition driver_types.h:43
int kernelExecTimeoutEnabled
Specified whether there is a run time limit on kernels.
Definition driver_types.h:61
int maxSurface2D[2]
Maximum 2D surface dimensions.
Definition driver_types.h:85
int memoryClockRate
Peak memory clock frequency in kilohertz.
Definition driver_types.h:104
size_t totalConstMem
Constant memory available on device in bytes.
Definition driver_types.h:52
int l2CacheSize
Size of L2 cache in bytes.
Definition driver_types.h:106
int pciBusID
PCI bus ID of the device.
Definition driver_types.h:96
int maxSurfaceCubemap
Maximum Cubemap surface dimensions.
Definition driver_types.h:89
int maxSurfaceCubemapLayered[2]
Maximum Cubemap layered surface dimensions.
Definition driver_types.h:90
int regsPerMultiprocessor
32-bit registers available per multiprocessor
Definition driver_types.h:114
int clockRate
Clock frequency in kilohertz.
Definition driver_types.h:51
int localL1CacheSupported
Device supports caching locals in L1.
Definition driver_types.h:111
int memoryBusWidth
Global memory bus width in bits.
Definition driver_types.h:105
int maxSurface2DLayered[3]
Maximum 2D layered surface dimensions.
Definition driver_types.h:88
int maxTexture2DMipmap[2]
Maximum 2D mipmapped texture dimensions.
Definition driver_types.h:72
int pciDomainID
PCI domain ID of the device.
Definition driver_types.h:98
int managedMemory
Device supports allocating managed memory on this system.
Definition driver_types.h:116
int maxTextureCubemapLayered[2]
Maximum Cubemap layered texture dimensions.
Definition driver_types.h:82
int maxTextureCubemap
Maximum Cubemap texture dimensions.
Definition driver_types.h:79
int tccDriver
1 if device is a Tesla device using TCC driver, 0 otherwise
Definition driver_types.h:99
int maxSurface1D
Maximum 1D surface size.
Definition driver_types.h:84